Present day data processing systems commonly employ cache memories for expediting processing execution that avoids reference to main memory. As such, the data stored in the cache is subject to frequent modification either by the same or by a different user process, so that the data in cache for one process may be invalid for another user process. For example, in the event of a context switch or a process switch, it is desirable to flush the cache, since the logical addresses within a single user process are unique, but can be duplicated between two processes. In the past, cache flush schemes have involved the scanning of each memory location in the cache and individually clearing each valid bit. Examples of schemes for clearing or flushing cache memories using this conventional technique are described in the U.S. Pat. No. 3,800,286; to Brown Lange et al. U.S. Pat. Nos. 3,845,474; Ready 3,840,862; Lange et al. 3,896,419 and Lange et al. 3,979,726. Unfortunately, the time involved in executing a separate cycle through the cache for each storage location, in order to flush the cache, is considerable and reduces processing speed.